Integrated circuits (ICs) typically are formed by depositing some combination of conductive, semiconductive, insulating, and barrier-forming materials on a semiconductor substrate, such as a doped silicon wafer. One common technique for producing an IC, known as "subtractive metallization," involves depositing a conductive or semiconductive layer on the substrate and then etching away a portion of the conductive layer to form a conductive pattern. A barrier layer usually separates the conductive layer from the semiconductor substrate to protect the substrate from contamination by the conductive material. In most cases, additional conductive or semiconductive layers are deposited over the original conductive layer. Each pair of adjacent conductive layers is separated by an insulating layer which, like the original conductive layer, is patterned to allow ohmic contact between the conductive layers.
Another common technique for producing an IC, known as "Damascene metallization," involves forming an insulating layer directly over the semiconductor substrate, etching the insulating layer to form an opening over a portion of the semiconductor substrate, depositing a barrier layer over the insulating layer and the opening, and then depositing a conductive material over the barrier layer. The opening in the insulating layer allows ohmic contact between the conductive layer and a portion of the semiconductor substrate. The barrier layer protects the semiconductor substrate from contamination by the conductive layer.
One problem with these semiconductor fabrication techniques is that etching the conductive layers produces unwanted topography on the surface of the semiconductor device for subsequent processing. Damascene processing has the potential of creating topography-free surfaces. The complexity of the topography increases with the number of additional layers. As a result, most semiconductor manufacturing processes include one or more planarization steps to remove topography from the surfaces of semiconductor devices.
Chemical mechanical polishing (CMP) is one very common type of planarization process. In general, a CMP process involves mounting the semiconductor device on a carrier or polishing head and pressing the surface of the device against a rotating polishing pad. A traditional slurry-based CMP process uses a standard polishing pad in combination with a liquid slurry that includes a chemically reactive agent and abrasive particles. Recently developed "slurryless" CMP processes use fixed-abrasive pads in conjunction with polishing liquids containing chemically reactive agents but no abrasive particles. A fixed-abrasive pad includes abrasive particles embedded within a containment media. A standard polishing pad has a durable surface with no embedded abrasive particles.
An effective CMP process not only provides a high polishing rate, but also provides a substrate surface that lacks small-scale roughness (i.e., is "finished") and that lacks large-scale topography (i.e., is "flat"). The polishing rate, finish, and flatness associated with a particular CMP process are determined by several factors, including the type of pad and the type of slurry used, the relative speed between the semiconductor substrate and the polishing pad, and the amount of pressure that forces the semiconductor substrate against the polishing pad.
Planarization of a semiconductor device formed by Damascene metallization usually involves a conventional Damascene CMP process. Damascene CMP techniques use standard polishing pads and "selective" or "nonselective" slurries. Nonselective slurries attempt to polish the conductive layer and the barrier layer simultaneously, leaving a perfectly planarized surface on which only the insulating layer and the conductive material in the trenches of the insulating layer are exposed. However, current semiconductor fabrication techniques usually produce devices with nonuniformities in the conductive layer, which leads to uneven removal time across the surface of the device. This combined with CMP within-wafer-nonuniformity (WIWNU) can lead to significant variation across the wafer-in dishing and erosion. As a result, the insulating layer becomes exposed at some areas on the device while thin layers of barrier and conductive materials remain on other areas of the device. Moreover, because conventional nonselective polishing techniques remove insulating, barrier, and conductive materials at similar rates, these nonuniformities in the surface of the semiconductor device leads to a phenomenon known as "metal thinning." Selective slurries cause dishing and erosion across the wafer.